We are glad to host a wide variety of speakers from academia, industry, and government. Please see below for an overview of the talks confirmed so far (speakers listed in alphatical order).

If you are interested in presenting as well, please reach out to us via e-mail ().


Hardware Reverse Engineering: A Vital Necessity Facing Tremendous Challenges
Olivier Thomas, Texplained, France
The semiconductor industry is one of the most evolving sector of the last 60 years. From the military dedicated simple chips to the nowadays extremely complex components embedded in everything, the heart of technology have quickly and intensely revolutionized our world. First used for piracy and anti-piracy activities, the Hardware Reverse Engineering has evolved along with the semiconductor development. From the very basic tools and processes of the 90’s made for recovering data from ICs, to the current automated solutions, hardware reverse engineering has become the method required for many purposes. Nowadays used for criminal investigations, backdoor research, IP infringement investigation, obsolete devices management, hardware security evaluation, etc. reversing chips brings together an ever-growing community. More advanced tools, more experience, more knowledge sharing will allow to face the future of reverse engineering, which is paved with many challenges due to the increase of complexity and protection of ICs and devices.


Real World Reverse Engineering
Nils Albartus & Julian Speith, MPI-SP, Germany


GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
Lilas Alrahis, New York University Abu Dhabi (NYUAD), UAE
Graph Neural Networks (GNNs) have shown great success in facilitating learning on graph-structured data, such as social networks, recommendation systems, and protein-protein interactions. Since electronic circuits can be represented naturally as graphs, GNNs provide great potential to advance Machine Learning (ML)-based methods for all aspects of electronic system design and Computer-Aided Design (CAD). This talk gives a deep dive on how to design and employ GNNs to learn the properties of circuits. Starting with a background on GNNs and their different classification tasks, moving to circuit-to-graph conversion, and finally to design and employment. Taking hardware security as a target application, this talk demonstrates how graph-based learning on circuits aids in representing and analyzing flattened/unstructured gate-level netlists.

Using Reverse Engineering Techniques to Build a Secure Open-Source IC
Leonid Azriel, Technion Haifa, Israel
Open-source IC is not a new concept. Nevertheless, usage of open-source by the hardware community has been limited until recently. In the last few years, the introduction of the RISC-V open architecture helped to bring fresh energy to open-source IC, and many new projects have emerged. In addition to many benefits in productivity and quality, the open-source model contributes to product security by following the Kerckhoff's principle of open algorithm. However, unlike in software, in the IC world there is a long way from the source to the finished product, and it is hard to guarantee that the product indeed implements the algorithm as advertised. In this talk, I will discuss possible schemes, methodologies and policies to verify the compliance of the integrated circuit to the claimed open source and how the reverse engineering techniques may help with this task.

Steffen Becker, MPI-SP, Germany


Accurate Integrated Circuit Layout Recovery Using Advanced Vision
Ann-Christin Bette, Infineon, Germany
Reverse engineering (RE) can turn data into value for owners of intellectual property (IP). In addition to detecting IP violations, recovering the layout of integrated circuits (IC) enables increased supply chain security and comprehensive failure analysis. Typically, current layout recovery methods are only reliable for technologies larger than 90 nm. Each new generation of technology leads to a higher error rate during process execution. We propose a monitoring framework based on end-to-end AI vision systems that support the failure analyst in executing and evaluating each physical RE process step. We are addressing the increasing Big Data challenge in RE by building adequate infrastructure for data, models, and code.

Deep Learning-based Analysis of Microscopic IC Images for Hardware Assurance
Cheng Deruo, Nanyang Technological University (NTU), Singapore
With the advancements in microscopic imaging, high-resolution digital images can be captured at each layer of manufactured ICs with proper sample preparation. It is then feasible to analyse the microscopic IC images to uncover the circuit components and their three-dimensional interconnections for function-level authentication before IC deployment. However, the huge amount of image data with unforeseeable image defects and variations poses great challenge to the image analysis process, where conventional approaches are incompetent. In this talk, we will share our latest research on analysing microscopic IC images with deep learning, which includes a Generative Adversarial Network-based model for identifying defective IC images without supervision and a Convolutional Neural Network-based framework for retrieving circuit information from microscopic IC images. We will also discuss the challenges we have been facing with the data-driven learning-based approaches and provide some possible solutions or research directions.

The Physical Verification Challenge for IoT-Security
Bernhard Lippmann, Infineon, Germany
The acceptance of today’s highly connected world through applications – ranging from autonomous driving, smart home, industrial internet, health care and cloud services, the evaluation of information created by IoT devices or authentication using ID or payment devices – requires built-in security solutions. Technically, this is implemented by a hardware root of trust. As traditional verification flows as used for many commercial products only handle function, reliability and safety aspects, a trusted design flow extends this by including consideration of hardware security in verification and certification. Consequently, without comprehensive trust throughout the globally distributed development and production flow, semiconductor manufacturers need to check that no malicious modification is inserted. Verification can be executed on physical devices extracted from the field. For this task, the multifaceted feature sets of today’s advanced security solutions require innovative physical analysis inspection methods.

Hardware Trust Through Physical Inspection
Matthias Ludwig, Infineon, Germany
Trust in microelectronics has become an acute issue, with the industry pursuing a globally distributed supply-chain in which possibly non-trustworthy actors are involved. The door for potentially malicious tampering in the form of counterfeiting or the inclusion of malicious modifications during hardware specification, design, manufacturing, and even recycling has been opened. To regain trust in the physical layers, new post-silicon verification and validation techniques are in demand. This talk elaborates ways to verify product integrity through physical inspection. First, a physical layout verification technique is introduced. The methodology and results to validate layout integrity are presented on a 40 nm test device. Furthermore, a novel anti-counterfeiting method on the silicon-level is presented and experimental results are shown.

Avi Mendelson, Technion Haifa, Israel


Fabrication-time Insertion of Hardware Trojan Horses
Samuel Pagliarini, Tallinn University of Technology (TalTech), Estonia
For more than almost two decades now, researchers have hypothesized that Hardware Trojan Horses can be inserted in integrated circuits (ICs) while they are being fabricated. These trojans are malicious circuits that typically aim to corrupt the computation being carried out by a chip or they may expose privileged data such as keys utilized in cryptography. Even though only a few real examples have been observed, the risk of a security breach due to hardware tampering has been in the hardware security community's focus for many years. In this talk, the practicality of a fabrication-time attack is going to be addressed. Tampering with a layout while having no additional information other than the layout itself has often been considered a colossal effort. However, with the help of the same tools utilized for chip design, it is shown that the attacker has the capability to modify a layout effortlessly. By doing so, many of the regarded security metrics are no longer valid and fabrication-time attacks become (more) feasible.

No Need for Reverse Engineering – Machine Learning Will Do It for Us
Jean-Pierre Seifert, TU Berlin, Germany
Usually, hardware vendors commonly believe that the ever-growing physical complexity of the integrated circuit (IC) designs can be a natural barrier against potential adversaries. In this work, we present a novel approach that can extract secrets without any knowledge of the IC’s layout, and independent from the employed memory technology as key storage. Using deep learning methods, we automate the – traditionally very labor-intensive – reverse-engineering and data extraction process. We showcase the potential of our approach by targeting keys on three different hardware platforms, which are utilized as RoT in different products.

Graph Neural Network for Circuit Netlist Analysis
Lin Tong, Nanyang Technological University (NTU), Singapore
Recovered circuit netlist, be it from ASIC or FPGA, contains vital information for hardware assurance of ICs. Conventional methods for analysing it usually require expert knowledge and are largely ad hoc and manual. Intuitively, a netlist can be analysed as a graph with logic gates as nodes and interconnections as edges. Recent advancement in AI/deep-learning on graphs, epitomized by the advent of Graph Neural Network (GNN), points to new ways of analysing circuit netlist from a data-driven perspective. In this talk, we will share our latest research in this area, where we follow a ‘divide-and-conquer’ approach. We will present our proposed GNN-based methods in solving the two fundamental problems involved in netlist analysis, namely netlist partition and netlist identification. We will discuss the advantages of using GNN as compared to using the conventional methods. We will also address the limitations of existing GNN and point to possible solutions.